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Overview

Exhibition

Join the Ecosystem Pavilion and reach approximately 1,000 of director level and above executives from our customers!!


The TSMC Open Innovation Platform® (OIP) Ecosystem Forum is a one-of-a-kind event that brings together the semiconductor design chain community and approximately 1,000 of director-level and above TSMC customer executives. The OIP Forum will feature a day-long, three-track technical conference along with an Ecosystem Pavilion that will host up to 80 member companies.

Date: September 13, 2017
 
Time: 8:00 am – 6:00 pm
 
Venue: Santa Clara Convention Center


Ecosystem Pavilion

The TSMC OIP Ecosystem Pavilion will accommodate up to 80 companies. Applications to join the Ecosystem Pavilion will be accepted beginning June 10. Space is available on a first-come, first-serve basis.

Booth size:
(A) 10'x20' booth per unit - $7,000
(B) 20'x20' booth per unit - $14,000
(C) 20'x40' booths exclusively for the Platinum and Gold Sponsors

Decoration:
(A) For 10'x20' booths: black pipe and drape for backdrop and two sides
(B) For 20'x20' booths: customized booth of your choice
(C) For 20'x40' booths: customized booth of your choice


Exhibit Details

A. The Ecosystem Pavilion (10' x 20' booth) includes:
One 10' x 20' exhibit space
Pipe and drape
Carpet
One (1) 6' draped table
Two (2) chairs
One (1) 500W outlet
One (1) waste basket
Cart service from decorating company (one-way)
Access to decorating company for materials handling (in excess of the cart service that is included with the registration), accessories, and other services – Note: these costs are not covered by TSMC

C. Exhibitor Pass:
  For each booth unit, exhibitors will receive 4 (booth staff included) complimentary passes. Additional exhibitor personnel can attend for a $300 registration fee per person.

D. Booth Setup Time:

1.) 20' x 40' and 20' x 20' booths
Set-up time: Tuesday, September 12, 10:30am - 5pm
Dismantle time: Wednesday, September 13, 6:30pm - 10pm

2.) 10' x 20' booths
Set-up time: Tuesday, September 12, 1pm - 5pm
Dismantle time: Wednesday, September 13, 6:30pm - 10pm


Call for Paper


Technical sessions are organized along three tracks (EDA, IP, and Design Services) with a total of 33, 30-minute presentations; 11 presentation per track. Every member company is eligible and encouraged to submit papers. All papers will be reviewed by a Technical Paper Review Committee and scored based on their merit and their ability to define how TSMC technology is embedded into your products or services.

Papers should be written around the following topics:

EDA IP Design Services
Application-specific design platform (HPC, Mobile, IoT, and Automotive)
7FF/FF+, 12FFC, 16FF+/FFC
28HPC/HPC+, 22ULP
Physical Implementation
Advanced Timing
Low Power Design
Extraction, EM/IR
Physical Verification
Simulation / Modeling
Custom/AMS/RF Design
CoWoS / InFO
IP Availability
IP Validation
TSMC9000/9000-A
NVM
Application IPs
Wearables & IoT
Automotive IP
Co-optimization of CPU, GPU, RTL based IP
Hard + Soft IP subsystems (PHY+controller, design, verification, integration)
ESL & high-level power estimation
Soft IP
Value-Chain Aggregator (VCA) Services
Design Center Alliance (DCA) Services
Other Services
- SER service
- ESD service
- ARM hardening


There is no charge to present. Abstracts are due June 16, 2017. For more information about paper submissions, please contact Mr. Tom Quan at tquan@tsmc.com.


Important Paper Submission Dates:

June 16 Abstract and speaker biography submission deadline
June 30 Notification of selected abstracts
August 1 Full draft presentation slide submission due
August 11 Final presentation slides (print version) due
September 1 Final presentation slides (speech version) due
September 4-8 Mandatory presentation rehearsal


Application Form

Please go to Call for Paper Submission and fill in the form to submit the abstract and speaker bio.


The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.